ECS Intranet:
Reliable Low Power Circuit Design Techniques

With CMOS transistor size scaling leakage power consumption becomes an increasing problem for electronics system design. Mobile devices spend most of their time in idle mode. Idle circuit power consumption has high impact on the battery life of these devices, which will limit their applications. Low power design techniques such as power gating and supply voltage scaling were proposed to reduce leakage power. However these techniques introduce noises to a system and makes it more susceptible to errors. There are three important design parameters in an pervasive system: performance, power consumption and reliability. Higher performance enables more sophisticated applications, low power consumption prolongs the battery life and high reliability is a necessary requirement for critical tasks. The aim of this project is to provide low cost and effective circuit design techniques to improve the reliability of low power designs.

Partners

• ARM

Funding

Principal Investigators

• sy08r

Other Investigators

• Professor David Flynn
• Professor Bashir M Al-Hashimi
• Dr. Harry Oldham
• Sachin Idgunji